Fabrication of semiconductor devices typically involves deposition and patterning of several layers of different materials. When several layers are deposited in a stack, stress characteristics of deposited layers become particularly important because highly stressed materials can lead to disruption in alignment of layers in a stack, buckling, delamination, and, ultimately, to patterning inaccuracy, and semiconductor device failure.
Most film deposition is associated with the introduction of residual stress in the deposited film due to both extrinsic factors (e.g., thermal expansion coefficient mismatch) and/or intrinsic factors (e.g., defects and/or dislocations within lattice). The stress can be either compressive or tensile depending, for instance, on the characteristics of the substrate, the type of film being deposited, its properties, the manner of its deposition, etc. Compressive stress in the deposited films can lead to blistering or buckling of the film whereas tensile stress may lead to film cracking. Additionally, the wafer distortion induced by these stresses can cause reliability issue in other device layers and, generally, adversely impact electrical and optical performance, as well as the mechanical integrity of the fabricated semiconductor device. Thus, in semiconductor device fabrication, film stress is a major concern of the device layer integration strategy.